DS92LV010A

ACTIVE

Bus LVDS 3.3/5.0-V single transceiver

Product details

Function Transceiver Protocols BLVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3, 5 Signaling rate (MBits) 100 Input signal LVDS, LVTTL Output signal LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Transceiver Protocols BLVDS Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3, 5 Signaling rate (MBits) 100 Input signal LVDS, LVTTL Output signal LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 8 29.4 mm² 4.9 x 6
  • Bus LVDS Signaling (BLVDS)
  • Designed for Double Termination Applications
  • Balanced Output Impedance
  • Lite Bus Loading 5pF Typical
  • Glitch Free Power Up/Down (Driver Disabled)
  • 3.3V or 5.0V Operation
  • ±1V Common Mode Range
  • ±100mV Receiver Sensitivity
  • High Signaling Rate Capability (Above 100 Mbps)
  • Low Power CMOS Design
  • Product Offered in 8 Lead SOIC Package
  • Industrial Temperature Range Operation

All trademarks are the property of their respective owners.

  • Bus LVDS Signaling (BLVDS)
  • Designed for Double Termination Applications
  • Balanced Output Impedance
  • Lite Bus Loading 5pF Typical
  • Glitch Free Power Up/Down (Driver Disabled)
  • 3.3V or 5.0V Operation
  • ±1V Common Mode Range
  • ±100mV Receiver Sensitivity
  • High Signaling Rate Capability (Above 100 Mbps)
  • Low Power CMOS Design
  • Product Offered in 8 Lead SOIC Package
  • Industrial Temperature Range Operation

All trademarks are the property of their respective owners.

The DS92LV010A is one in a series of transceivers designed specifically for the high speed, low power proprietary bus backplane interfaces. The device operates from a single 3.3V or 5.0V power supply and includes one differential line driver and one receiver. To minimize bus loading the driver outputs and receiver inputs are internally connected. The logic interface provides maximum flexibility as 4 separate lines are provided (DIN, DE, RE, and ROUT). The device also features flow through which allows easy PCB routing for short stubs between the bus pins and the connector. The driver has 10 mA drive capability, allowing it to drive heavily loaded backplanes, with impedance as low as 27 Ohms.

The driver translates between TTL levels (single-ended) to Low Voltage Differential Signaling levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition the differential signaling provides common mode noise rejection of ±1V.

The receiver threshold is ±100mV over a ±1V common mode range and translates the low voltage differential levels to standard (CMOS/TTL) levels.

The DS92LV010A is one in a series of transceivers designed specifically for the high speed, low power proprietary bus backplane interfaces. The device operates from a single 3.3V or 5.0V power supply and includes one differential line driver and one receiver. To minimize bus loading the driver outputs and receiver inputs are internally connected. The logic interface provides maximum flexibility as 4 separate lines are provided (DIN, DE, RE, and ROUT). The device also features flow through which allows easy PCB routing for short stubs between the bus pins and the connector. The driver has 10 mA drive capability, allowing it to drive heavily loaded backplanes, with impedance as low as 27 Ohms.

The driver translates between TTL levels (single-ended) to Low Voltage Differential Signaling levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition the differential signaling provides common mode noise rejection of ±1V.

The receiver threshold is ±100mV over a ±1V common mode range and translates the low voltage differential levels to standard (CMOS/TTL) levels.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 3
Type Title Date
* Data sheet DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver datasheet (Rev. E) 16 Apr 2013
Application note LVDS Signal Quality: Cable Drive Measurements using Eye Patterns Test Report #3 15 May 2004
Application note DS92LV010A Bus LVDS Transcvr Ushers New Era of High-Perf Backplane Design 15 May 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

DS92LV010A IBIS Model

SNLM035.ZIP (15 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Package Pins Download
SOIC (D) 8 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos