Packaging information
| Package | Pins LQFP (PZ) | 100 |
| Operating temperature range (°C) -40 to 125 |
| Package qty | Carrier 90 | JEDEC TRAY (5+1) |
Features for the TMS470MF06607
- High-Performance Automotive Grade Microcontroller with Safety Features
- Full Automotive Temperature Range
- ECC on Flash and SRAM
- CPU and Memory BIST (Built-In Self Test)
- ARM Cortex™-M3 32-Bit RISC CPU
- Efficient 1.2 DMIPS/MHz
- Optimized Thumb2 Instruction Set
- Memory Protection Unit (MPU)
- Open Architecture With Third-Party Support
- Built-In Debug Module
- Operating Features
- Up to 80MHz System Clock
- Single 3.3V Supply Voltage
- Integrated Memory
- 640KB Total Program Flash with ECC
- Support for Flash EEPROM Emulation
- 64K-Byte Static RAM (SRAM) with ECC
- Key Peripherals
- High-End Timer, MibADC, CAN, MibSPI
- Common TMS470M/570 Platform Architecture
- Consistent Memory Map across the family
- Real-Time Interrupt Timer (RTI)
- Digital Watchdog
- Vectored Interrupt Module (VIM)
- Cyclic Redundancy Checker (CRC)
- Frequency-Modulated Zero-Pin Phase-Locked Loop (FMZPLL)-Based Clock Module
- Oscillator and PLL clock monitor
- Up to 77 Peripheral IO pins
- 8 Dedicated GIO - w/ External Interrupts
- Programmable External Clock (ECLK)
- Communication Interfaces
- Two CAN ControllersOne with 32 mailboxes, one with 16Parity on mailbox RAM
- Two Multi-buffered Serial Peripheral Interface (MibSPI)12 total chip selects64 buffers with parity on eachOne with 4 bit parallel mode
- One Standard SPI Interface4 chip selectsEnable Pin
- Two UART (SCI) interfacesH/W Support for Local Interconnect Network (LIN 2.0)
- High-End Timer (HET)
- Up to 26 Programmable I/O Channels
- 64 Word Instruction RAM with parity
- 10-Bit Multi-Buffered ADCs (MibADC)
- Up to 16 ADC Input channels
- 64 Result FIFO Buffer with parity
- 1.55uS total conversion time
- Calibration and Self Test features
- On-Chip Scan-Base Emulation Logic
- IEEE Standard 1149.1 (JTAG) Test-Access Port and Boundary Scan
- Packages supported
- 144-Pin Plastic Quad Flatpack (PGE Suffix)
- 100-Pin Plastic Quad Flatpack (PZ Suffix)
- Green/Lead-Free
- Development Tools Available
- Development Boards
- Code Composer Studio™ Integrated Development Environment (IDE)
- HET Assembler and Simulator
- nowFlash™ Flash Programming Tool
- Community Reesources
All other trademarks are the property of their respective owners
Description for the TMS470MF06607
The TMS470MF06607 device is a member of the Texas Instruments TMS470M family of Automotive Grade 16/32-bit reduced instruction set computer (RISC) microcontrollers. The TMS470M microcontrollers offer high performance utilizing the high efficiency ARM Cortex™-M3 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency.
High-end embedded control applications demand more performance from their controllers while maintaining low costs. The TMS470M microcontroller architecture offers solutions to these performance and cost demands while maintaining low power consumption.
The TMS470MF06607 device contains the following:
- 16/32-Bit RISC CPU Core
- 640K-Byte Total Flash with SECDED ECC
- 512K-Byte Program Flash
- 128K- Byte Flash for additional program space or EEPROM Emulation
- 64K-Byte Static RAM (SRAM) with SECDED ECC
- Real-Time Interrupt Timer (RTI)
- Vectored Interrupt Module (VIM)
- Hardware built-in self-test (BIST) checkers for SRAM (MBIST) and CPU (LBIST)
- 64-bit Cyclic Redundancy Checker (CRC)
- Frequency-Modulated Zero-Pin Phase-Locked Loop (FMZPLL)-Based Clock Module With Prescaler
- Two Multi-buffered Serial Peripheral Interfaces (MibSPI)
- Two UARTs (SCI) with Local Interconnect Network Interfaces (LIN)
- Two CAN Controller (DCAN)
- High-End Timer (HET)
- External Clock Prescale (ECP) Module
- One 16-Channel 10-Bit Multi-Buffered ADC (MibADC)
- Error Signaling Module (ESM)
- Four Dedicated General-Purpose I/O (GIO) Pins and 47 (2 of them are muxed with JTAG pins) Additional Peripheral I/Os (100-Pin Package)
The TMS470M memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes. The SRAM on the TMS470M devices can be protected by means of ECC. This feature utilizes a single error correction and double error detection circuit (SECDED circuit) to detect and optionally correct single bit errors as well as detect all dual bit and some multi-bit errors. This is achieved by maintaining an 8-bit ECC checksum/code for each 64-bit double-word of memory space in a separate ECC RAM memory space.