Packaging information
| Package | Pins FCBGA (GJC) | 352 |
| Operating temperature range (°C) -40 to 105 |
| Package qty | Carrier 24 | JEDEC TRAY (5+1) |
Features for the SM320C6201-EP
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of –40°C to 105°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- High-Performance Fixed-Point Digital Signal Processor (DSP) SM320C6201
- 5-ns Instruction Cycle Time
- 200-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- 1600 MIPS
- VelociTI™ Advanced Very Long Instruction Word (VLIW) TMS320C62x™ DSP CPU Core
- Eight Independent Functional Units:
- Six Artihmetic Logic Units (ALUs) (32-/40-Bit)
- Two 16-Bit Multipliers (32-Bit Results)
- Load-Store Architecture With 32 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Eight Independent Functional Units:
- Instruction Set Features
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 32-Bit Address Range
- 8-Bit Overflow Protection
- Saturation
- Bit-Field Extract, Set, Clear
- Bit-Counting
- Normalization
- 1M-Bit On-Chip SRAM
- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency
- 32-Bit External Memory Interface (EMIF)
- Glueless Interface to Asynchronous Memories: SRAM and EPROM
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
- Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel
- 16-Bit Host-Port Interface (HPI)
- Access to Entire Memory Map
- Two Multichannel Buffered Serial Ports (McBSPs)
- Direct Interface to T1/E1, MVIP, SCSA Framers
- ST-Bus-Switching Compatible
- Up to 256 Channels Each
- AC97-Compatible
- Serial Peripheral Interface (SPI) Compatible (Motorola™)
- Two 32-Bit General-Purpose Timers
- Flexible Phase-Locked Loop (PLL) Clock Generator
- IEEE-1149.1 (JTAG
) Boundary-Scan Compatible - 352-Pin BGA Package (GJC Suffix)
- CMOS Technology
- 0.18-µm/5-Level Metal Process
- 3.3-V I/Os, 1.8-V Internal
VelociTI and TMS320C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, C6000, and C62x are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
The SM320C6201-EP device shall be referred to as C6201 throughout the remainder of this document.
C6000 is a trademark of Texas Instruments.
Description for the SM320C6201-EP
The TMS320C62x™ DSPs (including the SM320C6201-EP) are the fixed-point DSP family in the TMS320C6000 ™DSP platform. The C6201 device is based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. With performance of up to 1600 MIPS at a clock rate of 200 MHz, the C6201 offers cost-effective solutions to high-performance DSP programming challenges. The C6201 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6201 can produce two multiply-accumulates (MACs) per cycle—for a total of 466 million MACs per second (MMACS). The C62x™ DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The C6201 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory of the C6201 consists of two 32K-byte blocks of RAM for improved concurrency. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The C62x™ DSP has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.