Product details

Function Differential Additive RMS jitter (typ) (fs) 300 Output frequency (max) (MHz) 3500 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 30 Features 1:10 fanout Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type HSTL, LVPECL
Function Differential Additive RMS jitter (typ) (fs) 300 Output frequency (max) (MHz) 3500 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 30 Features 1:10 fanout Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVPECL Input type HSTL, LVPECL
LQFP (VF) 32 81 mm² 9 x 9
  • Distributes One Differential Clock Input Pair
    LVPECL/HSTL to 10 Differential LVPECL Clock Outputs
  • Fully Compatible With LVECL/LVPECL/HSTL
  • Single Supply Voltage Required, ±3.3-V or ±2.5-V Supply
  • Selectable Clock Input Through CLK_SEL
  • Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
  • VBB Reference Voltage Output for Single-Ended Clocking
  • Available in a 32-Pin LQFP Package
  • Frequency Range From DC to 3.5 GHz
  • Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111

  • Distributes One Differential Clock Input Pair
    LVPECL/HSTL to 10 Differential LVPECL Clock Outputs
  • Fully Compatible With LVECL/LVPECL/HSTL
  • Single Supply Voltage Required, ±3.3-V or ±2.5-V Supply
  • Selectable Clock Input Through CLK_SEL
  • Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
  • VBB Reference Voltage Output for Single-Ended Clocking
  • Available in a 32-Pin LQFP Package
  • Frequency Range From DC to 3.5 GHz
  • Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111

The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines.

The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP110 is characterized for operation from –40°C to 85°C.

The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines.

The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP110 is characterized for operation from –40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet Low-Voltage 1:10 LVPECL/HSTL With Selectable Input Clock Driver datasheet (Rev. D) 11 Jan 2011
Application note Clocking Design Guidelines: Unused Pins 19 Nov 2015
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) 17 Oct 2007
Application note Advantage of Using TI's Lowest Jitter Differential Clock Buffer 20 Aug 2003
Application note DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML 19 Feb 2003
Application note PCB Layout Guidelines for CDCLVP110 12 Jun 2002

Design & development

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Simulation model

CDCLVP110 IBIS Model (Rev. A)

SCAC032A.ZIP (32 KB) - IBIS Model
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PLLATINUMSIM-SW PLLatinum Sim Tool

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Supported products & hardware

Supported products & hardware

Products
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Clock jitter cleaners & synchronizers
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CDCDB2000 DB2000QL compliant 20-output clock buffer for PCIe® Gen 1 to Gen 5 CDCDB400 4-output clock buffer for PCIe® Gen 1 to Gen 6 CDCDB800 8-output clock buffer for PCIe® Gen 1 to Gen 6 CDCDB803 8-output clock buffer for PCIe® Gen 1 to Gen 6 with selectable SMBus addresses CDCLVC1102 Low jitter, 1:2 LVCMOS fan-out clock buffer CDCLVC1103 Low jitter, 1:3 LVCMOS fan-out clock buffer CDCLVC1104 Low jitter, 1:4 LVCMOS fan-out clock buffer CDCLVC1106 Low jitter, 1:6 LVCMOS fan-out clock buffer CDCLVC1108 Low jitter, 1:8 LVCMOS fan-out clock buffer CDCLVC1110 Low jitter, 1:10 LVCMOS fan-out clock buffer CDCLVC1112 Low jitter, 1:12 LVCMOS fan-out clock buffer CDCLVC1310 Universal input, 10-output low impedance LVCMOS buffer CDCLVD110 1-to-10 LVDS clock buffer up to 900-MHz with minimum skew for clock distribution CDCLVD110A 1-to-10 LVDS clock buffer up to 1100-MHz with minimum skew for clock distribution CDCLVD1204 Low jitter, 2-input selectable 1:4 universal-to-LVDS buffer CDCLVD1208 Low jitter, 2-input selectable 1:8 universal-to-LVDS buffer CDCLVD1212 Low jitter, 2-input selectable 1:12 universal-to-LVDS buffer CDCLVD1213 Low jitter, 1:4 universal-to-LVDS buffer with selectable output divider CDCLVD1216 Low jitter, 2-input selectable 1:16 universal-to-LVDS buffer CDCLVD2102 Low jitter, dual 1:2 universal-to-LVDS buffer CDCLVD2104 Low jitter, dual 1:4 universal-to-LVDS buffer CDCLVD2106 Low jitter, dual 1:6 universal-to-LVDS buffer CDCLVD2108 Low jitter, dual 1:8 universal-to-LVDS buffer CDCLVP110 1:10 LVPECL/HSTL to LVPECL clock driver CDCLVP1102 Low jitter 1:2 universal-to-LVPECL buffer CDCLVP111 1:10 LVPECL buffer with selectable input CDCLVP111-EP HiRel, 1:10 LVPECL buffer with selectable input CDCLVP111-SP 1:10 high speed clock buffer with selectable input clock driver CDCLVP1204 Low-jitter, two-input, selectable 1:4 universal-to-LVPECL buffer CDCLVP1208 Low jitter, 2-input selectable 1:8 universal-to-LVPECL buffer CDCLVP1212 Low jitter, 2-input selectable 1:12 universal-to-LVPECL buffer CDCLVP1216 Low jitter, 2-input selectable 1:16 universal-to-LVPECL buffer CDCLVP2102 Low jitter, dual 1:2 universal-to-LVPECL buffer CDCLVP2104 Low jitter, dual 1:4 universal-to-LVPECL buffer CDCLVP2106 Low jitter, dual 1:6 universal-to-LVPECL buffer CDCLVP2108 Low jitter, dual 1:8 universal-to-LVPECL buffer CDCLVP215 Dual 1:5 high speed LVPECL fan out buffer LMK00301 3-GHz, 10-output differential fanout buffer / level translator LMK00304 3.1-GHz differential clock buffer/level translator with 4 configurable outputs LMK00306 3.1-GHz differential clock buffer/level translator with 6 configurable outputs LMK00308 3.1-GHz differential clock buffer/level translator with 8 configurable outputs LMK00334 4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator LMK00334-Q1 Automotive 4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator LMK00338 8-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator LMK1C1102 2-channel output LVCMOS 1.8-V buffer LMK1C1103 3-channel output LVCMOS 1.8-V buffer LMK1C1104 4-channel output LVCMOS 1.8-V buffer LMK1C1106 6-channel output LVCMOS 1.8-V buffer LMK1C1108 8-channel output LVCMOS 1.8-V buffer LMK1D1204 4-channel output LVDS 1.8-V buffer LMK1D1204P 4-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer with pin control LMK1D1208 8-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer LMK1D1208I 8-channel output, 1.8-V, 2.5-V, and 3.3-V LVDS buffer with I²C LMK1D1208P 8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer with pin control LMK1D1212 12-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer LMK1D1216 16-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer LMK1D2102 Dual bank 2-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer LMK1D2104 Dual bank 4-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer LMK1D2106 Dual bank 6-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer LMK1D2108 Dual bank 8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer
Clock generators
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Hardware development
Evaluation board
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Software
Application software & framework
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IDE, configuration, compiler or debugger
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LQFP (VF) 32 View options

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