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The SN74GTL2006 is a 13-bit translator to interface between the 3.3-V LVTTL chipset I/O and the Xeon™ processor GTL-/GTL/GTL+ I/O. The device is designed for platform health management in dual-processor applications.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | SN74GTL2006 datasheet | 17 Dec 2004 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 26 Jul 2021 | ||
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| Application note | Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices | 10 May 2002 | ||
| User guide | GTLP/GTL Logic High-Performance Backplane Drivers Data Book (Rev. A) | 15 Sep 2001 | ||
| Selection guide | Advanced Bus Interface Logic Selection Guide | 09 Jan 2001 | ||
| Application note | GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A) | 01 Mar 1997 | ||
| Application note | Understanding Advanced Bus-Interface Products Design Guide | 01 May 1996 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | Download |
|---|---|---|
| TSSOP (PW) | 28 | View options |
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