SN65LVDS047

ACTIVE

Quad LVDS driver with flow-through pinout

Product details

Function Driver Protocols LVDS Number of transmitters 4 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal CMOS, LVTTL, TTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
Function Driver Protocols LVDS Number of transmitters 4 Number of receivers 0 Supply voltage (V) 3.3 Signaling rate (MBits) 400 Input signal CMOS, LVTTL, TTL Output signal LVDS Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • >400 Mbps (200 MHz) Signaling Rates
  • Flow-Through Pinout Simplifies PCB Layout
  • 300 ps Maximum Differential Skew
  • Propagation Delay Times 1.8 ns (Typical)
  • 3.3 V Power Supply Design
  • ±350 mV Differential Signaling
  • High Impedance on LVDS Outputs on Power Down
  • Conforms to TIA/EIA-644 LVDS Standard
  • Industrial Operating Temperature Range (–40°C to 85°C)
  • Available in SOIC and TSSOP Packages

  • >400 Mbps (200 MHz) Signaling Rates
  • Flow-Through Pinout Simplifies PCB Layout
  • 300 ps Maximum Differential Skew
  • Propagation Delay Times 1.8 ns (Typical)
  • 3.3 V Power Supply Design
  • ±350 mV Differential Signaling
  • High Impedance on LVDS Outputs on Power Down
  • Conforms to TIA/EIA-644 LVDS Standard
  • Industrial Operating Temperature Range (–40°C to 85°C)
  • Available in SOIC and TSSOP Packages

The SN65LVDS047 is a quad differential line driver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100- load when enabled.

The intended application of this device and signaling technique is for point-to-point and multi-drop baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

The SN65LVDS047 is characterized for operation from -40°C to 85°C.

The SN65LVDS047 is a quad differential line driver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100- load when enabled.

The intended application of this device and signaling technique is for point-to-point and multi-drop baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

The SN65LVDS047 is characterized for operation from -40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet LVDS Quad Differential Line Driver datasheet (Rev. B) 01 Dec 2003
Application note Introduction to HVDC Architecture and Solutions for Control and Protection (Rev. B) PDF | HTML 07 Sep 2021
Application brief LVDS to Improve EMC in Motor Drives 27 Sep 2018
Application brief How Far, How Fast Can You Operate LVDS Drivers and Receivers? 03 Aug 2018
Application brief How to Terminate LVDS Connections with DC and AC Coupling 16 May 2018
Technical article Applications of Low Voltage Differential Signaling (LVDS) in Multifunction and Ind PDF | HTML 24 Aug 2017
Application note An Overview of LVDS Technology 05 Oct 1998

Design & development

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Simulation model

SN65LVDS047 IBIS Model D PKG (Rev. A)

SLLC093A.ZIP (7 KB) - IBIS Model
Simulation model

SN65LVDS047 IBIS Model PW PKG

SLLC212.ZIP (7 KB) - IBIS Model
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Package Pins Download
SOIC (D) 16 View options
TSSOP (PW) 16 View options

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