The DS1776 is an octal PI-bus Transceiver. The A to B path is latched. B outputs are open
collector with series Schottky diode, ensuring minimum B output loading. B outputs also have ramped
rise and fall times (2.5 ns typical), ensuring minimum PI-bus ringing. B inputs have glitch
rejection circuitry, 4 ns typical.
Designed using Texas Instrumentss Bi-CMOS process for both low operating and disabled
power. AC performance is optimized for the PI-Bus inter-operability requirements.
The DS1776 is an octal latched transceiver and is intended to provide the electrical
interface to a high performance wired-or bus. This bus has a loaded characteristic impedance range
of 20Ω to 50Ω and is terminated on each end with a 30Ω to 40Ω resistor.
The DS1776 is an octal bidirectional transceiver with open collector B and TRI-STATE A
port output drivers. A latch function is provided for the A port signals. The B port output driver
is designed to sink 100 mA from 2V and features a controlled linear ramp to minimize crosstalk and
ringing on the bus.
A separate high level control voltage (VX) is provided to prevent
the A side output high level from exceeding future high density processor supply voltage levels.
For 5V systems, VX is tied to VCC.
The DS1776 is an octal PI-bus Transceiver. The A to B path is latched. B outputs are open
collector with series Schottky diode, ensuring minimum B output loading. B outputs also have ramped
rise and fall times (2.5 ns typical), ensuring minimum PI-bus ringing. B inputs have glitch
rejection circuitry, 4 ns typical.
Designed using Texas Instrumentss Bi-CMOS process for both low operating and disabled
power. AC performance is optimized for the PI-Bus inter-operability requirements.
The DS1776 is an octal latched transceiver and is intended to provide the electrical
interface to a high performance wired-or bus. This bus has a loaded characteristic impedance range
of 20Ω to 50Ω and is terminated on each end with a 30Ω to 40Ω resistor.
The DS1776 is an octal bidirectional transceiver with open collector B and TRI-STATE A
port output drivers. A latch function is provided for the A port signals. The B port output driver
is designed to sink 100 mA from 2V and features a controlled linear ramp to minimize crosstalk and
ringing on the bus.
A separate high level control voltage (VX) is provided to prevent
the A side output high level from exceeding future high density processor supply voltage levels.
For 5V systems, VX is tied to VCC.