Product details

Function General-purpose timer Iq (typ) (mA) 0.25 Rating Catalog Operating temperature range (°C) -40 to 125 Supply voltage (max) (V) 15 Supply voltage (min) (V) 2
Function General-purpose timer Iq (typ) (mA) 0.25 Rating Catalog Operating temperature range (°C) -40 to 125 Supply voltage (max) (V) 15 Supply voltage (min) (V) 2
PDIP (P) 8 92.5083 mm² 9.81 x 9.43 SOIC (D) 8 29.4 mm² 4.9 x 6 SOP (PS) 8 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Very low power consumption:
    • 1-mW typical at V DD = 5 V
  • Capable of operation in astable mode
  • CMOS output capable of swinging rail to rail
  • High output current capability
    • Sink: 100-mA typical
    • Source: 10-mA typical
  • Output fully compatible with CMOS, TTL, and MOS
  • Low supply current reduces spikes during output transitions
  • Single-supply operation from 2 V to 15 V
  • Functionally interchangeable with the NE555; has same pinout
  • ESD protection exceeds 1000 V per ANSI/ESDA/JEDEC JS-001
  • Available in Q-temp automotive
    • High-reliability automotive applications
    • Configuration control and print support
    • Qualification to automotive standards
  • Very low power consumption:
    • 1-mW typical at V DD = 5 V
  • Capable of operation in astable mode
  • CMOS output capable of swinging rail to rail
  • High output current capability
    • Sink: 100-mA typical
    • Source: 10-mA typical
  • Output fully compatible with CMOS, TTL, and MOS
  • Low supply current reduces spikes during output transitions
  • Single-supply operation from 2 V to 15 V
  • Functionally interchangeable with the NE555; has same pinout
  • ESD protection exceeds 1000 V per ANSI/ESDA/JEDEC JS-001
  • Available in Q-temp automotive
    • High-reliability automotive applications
    • Configuration control and print support
    • Qualification to automotive standards

The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS™ technology. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of a high input impedance, this device supports smaller timing capacitors than those supported by the NE555 or LM555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs must be tied to an appropriate logic level to prevent false triggering.

The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS™ technology. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of a high input impedance, this device supports smaller timing capacitors than those supported by the NE555 or LM555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs must be tied to an appropriate logic level to prevent false triggering.

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Technical documentation

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Type Title Date
* Data sheet TLC555 LinCMOS™ Technology Timer datasheet (Rev. J) PDF | HTML 27 Nov 2023
Circuit design Frequency-to-Voltage Conversion Circuit Using a 555 Timer 21 Sep 2023
Application note Considering TI Smart DACs As an Alternative to 555 Timers PDF | HTML 02 Sep 2021
More literature Design low-duty-cycle timer circuits 03 Oct 2016
Application note TLC555-Q1 Used as a Positive and Negative Charge Pump 25 May 2016
Application note Synchronizing Three or More UCC28950 Phase-Shifted, Full-Bridge Controllers 13 Sep 2011

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

TLC555 TINA-TI Astable Reference Design (Rev. B)

SLFM002B.TSC (100 KB) - TINA-TI Reference Design
Simulation model

TLC555 TINA-TI Mono Reference Design (Rev. B)

SLFM003B.TSC (102 KB) - TINA-TI Reference Design
Simulation model

TLC555 TINA-TI Spice Model

SLFM005.ZIP (9 KB) - TINA-TI Spice Model
Simulation model

TLC555x and TLC556x PSpice Model (Rev. E)

SLFJ002E.ZIP (25 KB) - PSpice Model
Calculation tool

TLC555CALC TLC555 Design Calculator

This spreadsheet calculates the complete design of a TLC555 timer-based astable circuit given the timing capacitance, on time, and desired duty cycle. Resistor values are calculated to the nearest 1% value.
Supported products & hardware

Supported products & hardware

Products
Real-time clocks (RTCs) & timers
TLC555 2.1-MHz, 250-µA, Low-Power Timer
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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Test report: PDF
Reference designs

TIDA-010085 — 24-VAC multi-channel solid state relay reference design using digital isolator

This reference design demonstrates a multi-channel solid state relay (SSR) using a single isolation. The design uses a multi-channel digital isolator with a single isolated power supply and common ground gate-drive circuit to control multiple SSRs independently. The design is rated for 24-VAC (...)
Design guide: PDF
Schematic: PDF
Package Pins Download
PDIP (P) 8 View options
SOIC (D) 8 View options
SOP (PS) 8 View options
TSSOP (PW) 14 View options

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