Product details

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 2 IOL (max) (mA) 32 Supply current (max) (µA) 10 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 2 IOL (max) (mA) 32 Supply current (max) (µA) 10 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
DSBGA (YZP) 6 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 6 8.12 mm² 2.9 x 2.8 SOT-5X3 (DRL) 6 2.56 mm² 1.6 x 1.6 SOT-SC70 (DCK) 6 4.2 mm² 2 x 2.1
  • Available in the Texas Instruments NanoFree Package
  • Supports 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Maximum tpd of 4.1 ns at 3.3 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Can Be Used as a Down Translator to Translate Inputs From a Maximum of 5.5 V Down to the VCC Level
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

  • Available in the Texas Instruments NanoFree Package
  • Supports 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Maximum tpd of 4.1 ns at 3.3 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Can Be Used as a Down Translator to Translate Inputs From a Maximum of 5.5 V Down to the VCC Level
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

The SN74LVC2G34 device is a dual buffer gate designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G34 device performs the Boolean function Y = A in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LVC2G34 device is a dual buffer gate designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G34 device performs the Boolean function Y = A in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Pin-for-pin with same functionality to the compared device
SN74AUP2G07 ACTIVE 2-ch, 0.8-V to 3.6-V low power buffers with open-drain outputs Smaller voltage range (0.8V to 3.6V), longer average propagation delay (8ns), lower average drive strength (4mA)
Same functionality with different pin-out to the compared device
SN74AUP2G34 ACTIVE 2-ch, 0.8-V to 3.6-V low power buffers Smaller voltage range (0.8V to 3.6V), longer average propagation delay (8ns), lower average drive strength (4mA)

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 27
Type Title Date
* Data sheet SN74LVC2G34 Dual Buffer Gate datasheet (Rev. J) PDF | HTML 30 Oct 2015
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Simulation model

HSPICE MODEL OF SN74LVC2G34

SCEJ194.ZIP (87 KB) - HSpice Model
Simulation model

SN74LVC2G34 Behavioral SPICE Model

SCEM610.ZIP (7 KB) - PSpice Model
Simulation model

SN74LVC2G34 IBIS Model (Rev. B)

SCEM255B.ZIP (45 KB) - IBIS Model
Reference designs

TIDA-010054 — Bi-directional, dual active bridge reference design for level 3 electric vehicle charging stations

This reference design provides an overview on the implementation of a single-phase dual active bridge (DAB) DC/DC converter. DAB topology offers advantages like soft-switching commutations, a decreased number of devices and high efficiency. The design is beneficial where power density, cost, (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00420 — ADC-based, digitally-isolated, wide-input, 16-channel, AC/DC binary input reference design

This reference design showcases a cost-optimized and scalable ADC-based AC/DC binary input module (BIM) architecture with reinforced isolation. The 16 channels of a 10- or 12-bit SAR ADC are used for sensing multiple binary inputs. The op amps, in addition to keeping the cost per-channel low, (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-010065 — High-efficiency, low-emission, isolated DC/DC converter-based analog input module reference design

This reference design is a simplified architecture for generating an isolated power supply for isolated amplifiers for measuring isolated voltages and currents. A fully integrated DC/DC converter with reinforced isolation operating from a 5-V input with configurable 5-V or 5.4-V output (headroom (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00653 — Non-Isolated Bi-Directional Converter Reference Design for Battery Charging Applications

TIDA-00653 is a non-isolated 48 to 12-V bi-directional converter reference design for 48V battery applications enabled by the UCD3138 digital power controller. The design has the flexibility to work in either a ZVS transition-mode topology to optimize light-load efficiency, or a hard-switching (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-010055 — Non-isolated power architecture with diagnostics reference design for protection relay modules

This reference design showcases non-isolated power supply architectures for protection relays with analog input/output and communication modules generated from 5-, 12-, or 24-V DC input. To generate the power supplies the design uses DC/DC converters with an integrated FET, a power module with an (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-010011 — High efficiency power supply architecture reference design for protection relay processor module

This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
Design guide: PDF
Schematic: PDF
Reference designs

TIDA-00609 — Self-Booting Audio System

The purpose of this reference design is to provide hardware and software tools that can be used as reference for audio systems. The new revision of the PurePath™ Console Motherboard (Rev F) adds stand-alone self-booting capabilities to allow making compelling demos with any evaluation module (...)
Test report: PDF
Schematic: PDF
Package Pins Download
DSBGA (YZP) 6 View options
SOT-23 (DBV) 6 View options
SOT-5X3 (DRL) 6 View options
SOT-SC70 (DCK) 6 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos