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SN74LV126A

ACTIVE

4-ch, 2-V to 5.5-V buffers with 3-state outputs

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Data sheet

SN74LV126A

ACTIVE
Data sheet Order now

Product details

Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 16 Supply current (max) (µA) 20 IOH (max) (mA) -16 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 IOL (max) (mA) 16 Supply current (max) (µA) 20 IOH (max) (mA) -16 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4
  • 2V to 5.5V VCC operation
  • Maximum tpd of 6.5ns at 5V
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
  • Ioff supports live insertion, partial power down mode, and back drive protection
  • Support mixed-mode voltage operation on all ports
  • Latch-up performance exceeds 250mAper JESD 17
  • 2V to 5.5V VCC operation
  • Maximum tpd of 6.5ns at 5V
  • Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
  • Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
  • Ioff supports live insertion, partial power down mode, and back drive protection
  • Support mixed-mode voltage operation on all ports
  • Latch-up performance exceeds 250mAper JESD 17

The SN74LV126A quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.

These quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.

The SN74LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

The SN74LV126A quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.

These quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.

The SN74LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
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Technical documentation

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* Data sheet SN74LV126A Quadruple Bus Buffer Gates With 3-State Outputs datasheet (Rev. J) PDF | HTML 04 Apr 2024

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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Simulation model

SN74LV126A Behavioral SPICE Model

SCEM656.ZIP (7 KB) - PSpice Model
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Simulation model

SN74LV126A IBIS Model

SCEM127.ZIP (18 KB) - IBIS Model
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Package Pins Download
SOIC (D) 14 View options
SOP (NS) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
TVSOP (DGV) 14 View options
TI's Standard Terms and Conditions for Evaluation Items apply.

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