Product details

Technology family GTL Applications MDIO, PMBus, SDIO, SMBus Rating Catalog Operating temperature range (°C) -40 to 85
Technology family GTL Applications MDIO, PMBus, SDIO, SMBus Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • Provides Bidirectional Voltage Translation With No Direction Control Required
  • Allows Voltage Level Translation From 1 V up to 5 V
  • Provides Direct Interface With GTL, GTL+, LVTTL/TTL, and 5-V CMOS Levels
  • Low On-State Resistance Between Input and Output Pins (Sn/Dn)
  • Supports Hot Insertion
  • No Power Supply Required — Will Not Latch Up
  • 5-V-Tolerant Inputs
  • Low Standby Current
  • Flow-Through Pinout for Ease of Printed Circuit Board Trace Routing
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-4)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • Bidirectional or Unidirectional Applications Requiring Voltage-Level Translation From Any Voltage (1 V to 5 V) to Any Voltage (1 V to 5 V)
    • Low Voltage Processor I2C Port Translation to 3.3-V and/or 5-V I2C Bus Signal Levels
    • GTL/GTL+ Translation to LVTTL/TTL Signal Levels

  • Provides Bidirectional Voltage Translation With No Direction Control Required
  • Allows Voltage Level Translation From 1 V up to 5 V
  • Provides Direct Interface With GTL, GTL+, LVTTL/TTL, and 5-V CMOS Levels
  • Low On-State Resistance Between Input and Output Pins (Sn/Dn)
  • Supports Hot Insertion
  • No Power Supply Required — Will Not Latch Up
  • 5-V-Tolerant Inputs
  • Low Standby Current
  • Flow-Through Pinout for Ease of Printed Circuit Board Trace Routing
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-4)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • Bidirectional or Unidirectional Applications Requiring Voltage-Level Translation From Any Voltage (1 V to 5 V) to Any Voltage (1 V to 5 V)
    • Low Voltage Processor I2C Port Translation to 3.3-V and/or 5-V I2C Bus Signal Levels
    • GTL/GTL+ Translation to LVTTL/TTL Signal Levels

The GTL2010 provides ten NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage translations any voltage (1 V to 5 V) to any voltage (1 V to 5 V).

When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by the pullup resistors.

All transistors in the GTL2010 have the same electrical characteristics, and there is minimal deviation from one output to another in voltage or propagation delay. This offers superior matching over discrete transistor voltage-translation solutions where the fabrication of the transistors is not symmetrical. With all transistors being identical, the reference transistor (SREF/DREF) can be located on any of the other ten matched Sn/Dn transistors, allowing for easier board layout. The translator transistors with integrated ESD circuitry provides excellent ESD protection.

The GTL2010 provides ten NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference transistor (SREF and DREF). The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage translations any voltage (1 V to 5 V) to any voltage (1 V to 5 V).

When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by the pullup resistors.

All transistors in the GTL2010 have the same electrical characteristics, and there is minimal deviation from one output to another in voltage or propagation delay. This offers superior matching over discrete transistor voltage-translation solutions where the fabrication of the transistors is not symmetrical. With all transistors being identical, the reference transistor (SREF/DREF) can be located on any of the other ten matched Sn/Dn transistors, allowing for easier board layout. The translator transistors with integrated ESD circuitry provides excellent ESD protection.

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Technical documentation

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Type Title Date
* Data sheet GTL2010 datasheet 16 Feb 2006
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
User guide GTLP/GTL Logic High-Performance Backplane Drivers Data Book (Rev. A) 15 Sep 2001
Selection guide Advanced Bus Interface Logic Selection Guide 09 Jan 2001
Application note GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A) 01 Mar 1997
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
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Evaluation board

14-24-NL-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin non-leaded packages

14-24-NL-LOGIC-EVM is a flexible evaluation module (EVM) designed to support any logic or translation device that has a 14-pin to 24-pin BQA, BQB, RGY, RSV, RJW or RHL package.

User guide: PDF | HTML
Not available on TI.com
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TSSOP (PW) 24 View options

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