SN74AVCH2T45

ACTIVE

Dual-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation Aan 3-State Outputs

A newer version of this product is available

open-in-new Compare alternates
Drop-in replacement with upgraded functionality to the compared device
SN74AXCH2T45 ACTIVE 2-bit 0.65V to 3.6V AXC dual-supply bus transciever with bus-hold Pin-to-pin upgrade with a wider voltage range and improved performance

SN74AVCH2T45

ACTIVE

Product details

Technology family AVC Applications GPIO, I2S Bits (#) 2 High input voltage (min) (V) 0.8 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 500 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 20 Features Bus-hold, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AVC Applications GPIO, I2S Bits (#) 2 High input voltage (min) (V) 0.8 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 500 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 20 Features Bus-hold, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type Balanced CMOS, Push-Pull Rating Catalog Operating temperature range (°C) -40 to 85
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Available in the Texas Instruments NanoFree Package
  • VCC Isolation
  • 2-Rail Design
  • I/Os are 4.6 V Tolerant
  • Partial Power-Down-Mode Operation
  • Bus Hold on Data Inputs
  • Maximum Data Rates
    • 500 Mbps (1.8 V to 3.3 V)
    • 320 Mbps (< 1.8 V to 3.3 V)
    • 320 Mbps (Level-Shifting to 2.5 V or 1.8 V)
    • 280 Mbps (Level-Shifting to 1.5 V)
    • 240 Mbps (Level-Shifting to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
  • Available in the Texas Instruments NanoFree Package
  • VCC Isolation
  • 2-Rail Design
  • I/Os are 4.6 V Tolerant
  • Partial Power-Down-Mode Operation
  • Bus Hold on Data Inputs
  • Maximum Data Rates
    • 500 Mbps (1.8 V to 3.3 V)
    • 320 Mbps (< 1.8 V to 3.3 V)
    • 320 Mbps (Level-Shifting to 2.5 V or 1.8 V)
    • 280 Mbps (Level-Shifting to 1.5 V)
    • 240 Mbps (Level-Shifting to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22

This 2-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A ports are designed to track VCCA and accepts any supply voltage from 1.2 V to 3.6 V. The B ports are designed to track VCCB and accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation and level-shifting between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVCH2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR pin) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The SN74AVCH2T45 features active bus-hold circuitry, which holds unused or un-driven inputs at a valid logic state. TI does not recommend using pull-up or pull-down resistors with the bus-hold circuitry.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then both outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.

Active bus-hold circuitry holds unused or un-driven inputs at a valid logic state. NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This 2-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A ports are designed to track VCCA and accepts any supply voltage from 1.2 V to 3.6 V. The B ports are designed to track VCCB and accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation and level-shifting between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVCH2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR pin) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The SN74AVCH2T45 features active bus-hold circuitry, which holds unused or un-driven inputs at a valid logic state. TI does not recommend using pull-up or pull-down resistors with the bus-hold circuitry.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, then both outputs are in the high-impedance state. The bus-hold circuitry on the powered-up side always stays active.

Active bus-hold circuitry holds unused or un-driven inputs at a valid logic state. NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Download View video with transcript Video

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Evaluation board

AVCLVCDIRCNTRL-EVM — Generic EVM for Direction-Controlled Bidirectional Translation Device Supporting AVC and LVC

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

User guide: PDF
Not available on TI.com
Simulation model

SN74AVCH2T45 IBIS Model (Rev. B)

SCEM433B.ZIP (118 KB) - IBIS Model
Package Pins Download
DSBGA (YZP) 8 View options
SSOP (DCT) 8 View options
VSSOP (DCU) 8 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos