Product details

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 48 IOH (max) (mA) -12 Input type TTL Output type TTL Features Very high speed (tpd 5-10ns) Technology family BCT Rating Military Operating temperature range (°C) -55 to 125
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 48 IOH (max) (mA) -12 Input type TTL Output type TTL Features Very high speed (tpd 5-10ns) Technology family BCT Rating Military Operating temperature range (°C) -55 to 125
CDIP (JT) 24 221.44 mm² 32 x 6.92 LCCC (FK) 28 130.6449 mm² 11.43 x 11.43
  • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ
  • Bus Transceivers/Registers
  • Independent Registers and Enables for A and B Buses
  • Multiplexed Real-Time and Stored Data
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

  • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ
  • Bus Transceivers/Registers
  • Independent Registers and Enables for A and B Buses
  • Multiplexed Real-Time and Stored Data
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’BCT646 devices.

Output-enable (OE)\ and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either register or in both.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus will receive data when OE\ is low. In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.

These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’BCT646 devices.

Output-enable (OE)\ and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either register or in both.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus will receive data when OE\ is low. In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.

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Technical documentation

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Type Title Date
* Data sheet SN54BCT646, SN74BCT646 datasheet (Rev. D) 03 May 2004
* SMD SN54BCT646 SMD 5962-91555 21 Jun 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996

Design & development

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CDIP (JT) 24 View options
LCCC (FK) 28 View options

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