Home Logic & voltage translation Flip-flops, latches & registers D-type flip-flops
Home
Logic & voltage translation
Flip-flops, latches & registers
D-type flip-flops

SN54AHCT374

ACTIVE

Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs

Order now
Data sheet

SN54AHCT374

ACTIVE
Data sheet Order now

Product details

Number of channels 8 Technology family AHCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 8 Technology family AHCT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 70 IOL (max) (mA) 8 IOH (max) (mA) -8 Supply current (max) (µA) 40 Features Balanced outputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 20 167.464 mm² 24.2 x 6.92 CFP (W) 20 90.5828 mm² 13.09 x 6.92 LCCC (FK) 20 79.0321 mm² 8.89 x 8.89
  • Inputs are TTL-Voltage compatible
  • Latch-up performance exceeds 250 mA per JESD 17
  • Inputs are TTL-Voltage compatible
  • Latch-up performance exceeds 250 mA per JESD 17

The ’AHCT374 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels of the data (D) inputs.

The ’AHCT374 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels of the data (D) inputs.
open-in-new Find other D-type flip-flops
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Similar functionality to the compared device
NEW SN74LV2T74-EP ACTIVE Enhanced-product dual D-type flip-flops with clear, preset and integrated level shifter Voltage range (1.65V to 5.5V), voltage translation capable

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 21
Type Title Date
* Data sheet SNx4AHCT374 Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs datasheet (Rev. M) PDF | HTML 20 Apr 2023
* SMD SN54AHCT374 SMD 5962-96865 21 Jun 2016
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 Dec 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
Product overview Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Oct 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Package Pins Download
CDIP (J) 20 View options
CFP (W) 20 View options
LCCC (FK) 20 View options
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos