Product details

Function Single-ended Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 200 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 100 Features Pin control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVTTL Input type LVTTL
Function Single-ended Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 200 Number of outputs 10 Output supply voltage (V) 2.5, 3.3 Core supply voltage (V) 2.5, 3.3 Output skew (ps) 100 Features Pin control Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVTTL Input type LVTTL
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • High-Performance 1:10 Clock Driver
  • Pin-to-Pin Skew < 100 ps at VDD 3.3 V
  • VDD Range = 2.3 V to 3.6 V
  • Input Clock Up To 200 MHz (See Figure 7)
  • Operating Temperature Range -40°C to 85°C
  • Output Enable Glitch Suppression
  • Distributes One Clock Input to Two Banks of Five Outputs
  • Packaged in 24-Pin TSSOP
  • Pin-to-Pin Compatible to the CDCVF2310,
    Except the R = 22- Series Damping
    Resistors at Yn
  • APPLICATIONS
    • General-Purpose Applications

  • High-Performance 1:10 Clock Driver
  • Pin-to-Pin Skew < 100 ps at VDD 3.3 V
  • VDD Range = 2.3 V to 3.6 V
  • Input Clock Up To 200 MHz (See Figure 7)
  • Operating Temperature Range -40°C to 85°C
  • Output Enable Glitch Suppression
  • Distributes One Clock Input to Two Banks of Five Outputs
  • Packaged in 24-Pin TSSOP
  • Pin-to-Pin Compatible to the CDCVF2310,
    Except the R = 22- Series Damping
    Resistors at Yn
  • APPLICATIONS
    • General-Purpose Applications

The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.

The CDCVF310 is characterized for operation from -40°C to 85°C.

The CDCVF310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.

The CDCVF310 is characterized for operation from -40°C to 85°C.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 1
Type Title Date
* Data sheet 2.5-V to 3.3-V High-Performance Clock Buffer datasheet (Rev. B) 22 Jan 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation model

CDCVF310 IBIS Model (Rev. A)

SCAC058A.ZIP (22 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Package Pins Download
TSSOP (PW) 24 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos