CDC2510C is not recommended for new designs
Although this product continues to be in production to support previous designs, we don't recommend it for new designs. Consider one of these alternates:
open-in-new Compare alternates
Pin-for-pin with same functionality to the compared device
CDCVF2510 ACTIVE 3.3-V phase-lock loop clock driver with 10 outputs for DRAM applications Can achieve better performance

Product details

Function Zero-delay Output frequency (max) (MHz) 125 Number of outputs 10 Core supply voltage (V) 3.3 Output skew (ps) 250 Operating temperature range (°C) to Rating Catalog
Function Zero-delay Output frequency (max) (MHz) 125 Number of outputs 10 Core supply voltage (V) 3.3 Output skew (ps) 250 Operating temperature range (°C) to Rating Catalog
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • Use CDCVF2510A as a Replacement for this Device
  • Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2
  • Spread Spectrum Clock Compatible
  • Operating Frequency 25 MHz to 125 MHz
  • Static tPhase Error Distribution at 66 MHz to 100 MHz is ±150 ps
  • Drop-In Replacement for TI CDC2510A With Enhanced Performance
  • Jitter (cyc - cyc) at 66 MHz to 100 MHz is |100 ps|
  • Available in Plastic 24-Pin TSSOP
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of Ten Outputs
  • External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
  • On-Chip Series Damping Resistors
  • No External RC Network Required
  • Operates at 3.3 V
  • Use CDCVF2510A as a Replacement for this Device
  • Designed to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2
  • Spread Spectrum Clock Compatible
  • Operating Frequency 25 MHz to 125 MHz
  • Static tPhase Error Distribution at 66 MHz to 100 MHz is ±150 ps
  • Drop-In Replacement for TI CDC2510A With Enhanced Performance
  • Jitter (cyc - cyc) at 66 MHz to 100 MHz is |100 ps|
  • Available in Plastic 24-Pin TSSOP
  • Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
  • Distributes One Clock Input to One Bank of Ten Outputs
  • External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input
  • On-Chip Series Damping Resistors
  • No External RC Network Required
  • Operates at 3.3 V

The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC = 3.3 V . It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2510C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The CDC2510C is characterized for operation from 0°C to 85°C.

For application information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039).

The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC = 3.3 V . It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDC2510C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The CDC2510C is characterized for operation from 0°C to 85°C.

For application information refer to application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (literature number SCAA039).

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 1
Type Title Date
* Data sheet CDC2510C: 3.3-V Phase-Lock Loop Clock Driver datasheet (Rev. A) 02 Dec 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Package Pins Download
TSSOP (PW) 24 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos