Product details

Frequency (MHz) 48 Flash memory (kByte) 384 RAM (kByte) 32 Number of GPIOs 53, 94 Features Hercules high-performance microcontroller Operating temperature range (°C) to SPI 2
Frequency (MHz) 48 Flash memory (kByte) 384 RAM (kByte) 32 Number of GPIOs 53, 94 Features Hercules high-performance microcontroller Operating temperature range (°C) to SPI 2
LQFP (PGE) 144 484 mm² 22 x 22 LQFP (PZ) 100 256 mm² 16 x 16
  • High-Performance Static CMOS Technology
  • TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
    • 24-MHz System Clock (48-MHz Pipeline)
    • Independent 16/32-Bit Instruction Set
    • Open Architecture With Third-Party Support
    • Built-In Debug Module
  • Integrated Memory
    • 384K-Byte Program Flash
      • Three Banks With 18 Contiguous Sectors
    • 32K-Byte Static RAM (SRAM)
  • Operating Features
    • Core Supply Voltage (VCC): 1.71 V to 2.05 V
    • I/O Supply Voltage (VCCIO): 3.0 V to 3.6 V
    • Low-Power Modes: STANDBY and HALT
    • Extended Industrial Temperature Range
  • 470+ System Module
    • 32-Bit Address Space Decoding
    • Bus Supervision for Memory/Peripherals
    • Analog Watchdog (AWD) Timer
    • Enhanced Real-Time Interrupt (RTI)
    • Interrupt Expansion Module (IEM)
    • System Integrity and Failure Detection
  • Direct Memory Access (DMA) Controller
    • 32 Control Packets and 16 Channels
  • Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler
    • Multiply-by-4 or -8 Internal ZPLL Option
    • ZPLL Bypass Mode
  • Expansion Bus Module (EBM) (PGE Package)
    • Supports 8- and 16-Bit Expansion Bus Memory Interface Mappings
    • 40 I/O Expansion Bus Pins
  • Ten Communication Interfaces:
    • Two Serial Peripheral Interfaces (SPIs)
      • 255 Programmable Baud Rates
    • Two Serial Communication Interfaces (SCIs)
      • 224 Selectable Baud Rates
      • Asynchronous/Isosynchronous Modes
    • Two Standard CAN Controllers (SCC)
      • 16-Mailbox Capacity
      • Fully Compliant With CAN Protocol, Version 2.0B
    • Class II Serial Interface B (C2SIb)
      • Normal 10.4 Kbps and 4X Mode 41.6 Kbps
    • Three Inter-Integrated Circuit (I2C) Modules (See I2C Notes in TMS470R1A384 Silicon Errata, Literature Number SPNZ148)
      • Multi-Master and Slave Interfaces
      • Up to 400 Kbps (Fast Mode)
      • 7- and 10-Bit Address Capability
  • High-End Timer (HET)
    • 12 Programmable I/O Channels:
      • 12 High-Resolution Pins
    • High-Resolution Share Feature (XOR)
    • High-End Timer RAM
      • 64-Instruction Capacity
  • External Clock Prescale (ECP) Module
    • Programmable Low-Frequency External Clock (CLK)
  • 12-Channel 10-Bit Multi-Buffered Analog-to-Digital Converter (MibADC)
    • 32-Word FIFO Buffer
    • Single- or Continuous-Conversion Modes
    • 1.55-µs Minimum Sample/Conversion Time
    • Calibration Mode and Self-Test Features
  • 55 Dedicated General-Purpose I/O (GIO) Pins and 39 Additional Peripheral I/Os (PGE)
  • 14 Dedicated General-Purpose I/O (GIO) Pins and 39 Additional Peripheral I/Os (PZ)
  • Flexible Interrupt Handling
  • Eight External Interrupts
  • On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1(1) (JTAG) Test-Access Port
  • 144-Pin Plastic Low-Profile Quad Flatpack (PGE Suffix)
  • 100-Pin Plastic Low-Profile Quad Flatpack (PZ Suffix)

(1) The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not supported on this device.
(2) Throughout the remainder of this document, the TMS470R1A384 is referred to as either the full device name or as A384.
(3) SAE Standard J1850 Class B Data Communication Network Interface.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All other trademarks are the property of their respective owners.

  • High-Performance Static CMOS Technology
  • TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
    • 24-MHz System Clock (48-MHz Pipeline)
    • Independent 16/32-Bit Instruction Set
    • Open Architecture With Third-Party Support
    • Built-In Debug Module
  • Integrated Memory
    • 384K-Byte Program Flash
      • Three Banks With 18 Contiguous Sectors
    • 32K-Byte Static RAM (SRAM)
  • Operating Features
    • Core Supply Voltage (VCC): 1.71 V to 2.05 V
    • I/O Supply Voltage (VCCIO): 3.0 V to 3.6 V
    • Low-Power Modes: STANDBY and HALT
    • Extended Industrial Temperature Range
  • 470+ System Module
    • 32-Bit Address Space Decoding
    • Bus Supervision for Memory/Peripherals
    • Analog Watchdog (AWD) Timer
    • Enhanced Real-Time Interrupt (RTI)
    • Interrupt Expansion Module (IEM)
    • System Integrity and Failure Detection
  • Direct Memory Access (DMA) Controller
    • 32 Control Packets and 16 Channels
  • Zero-Pin Phase-Locked Loop (ZPLL)-Based Clock Module With Prescaler
    • Multiply-by-4 or -8 Internal ZPLL Option
    • ZPLL Bypass Mode
  • Expansion Bus Module (EBM) (PGE Package)
    • Supports 8- and 16-Bit Expansion Bus Memory Interface Mappings
    • 40 I/O Expansion Bus Pins
  • Ten Communication Interfaces:
    • Two Serial Peripheral Interfaces (SPIs)
      • 255 Programmable Baud Rates
    • Two Serial Communication Interfaces (SCIs)
      • 224 Selectable Baud Rates
      • Asynchronous/Isosynchronous Modes
    • Two Standard CAN Controllers (SCC)
      • 16-Mailbox Capacity
      • Fully Compliant With CAN Protocol, Version 2.0B
    • Class II Serial Interface B (C2SIb)
      • Normal 10.4 Kbps and 4X Mode 41.6 Kbps
    • Three Inter-Integrated Circuit (I2C) Modules (See I2C Notes in TMS470R1A384 Silicon Errata, Literature Number SPNZ148)
      • Multi-Master and Slave Interfaces
      • Up to 400 Kbps (Fast Mode)
      • 7- and 10-Bit Address Capability
  • High-End Timer (HET)
    • 12 Programmable I/O Channels:
      • 12 High-Resolution Pins
    • High-Resolution Share Feature (XOR)
    • High-End Timer RAM
      • 64-Instruction Capacity
  • External Clock Prescale (ECP) Module
    • Programmable Low-Frequency External Clock (CLK)
  • 12-Channel 10-Bit Multi-Buffered Analog-to-Digital Converter (MibADC)
    • 32-Word FIFO Buffer
    • Single- or Continuous-Conversion Modes
    • 1.55-µs Minimum Sample/Conversion Time
    • Calibration Mode and Self-Test Features
  • 55 Dedicated General-Purpose I/O (GIO) Pins and 39 Additional Peripheral I/Os (PGE)
  • 14 Dedicated General-Purpose I/O (GIO) Pins and 39 Additional Peripheral I/Os (PZ)
  • Flexible Interrupt Handling
  • Eight External Interrupts
  • On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1(1) (JTAG) Test-Access Port
  • 144-Pin Plastic Low-Profile Quad Flatpack (PGE Suffix)
  • 100-Pin Plastic Low-Profile Quad Flatpack (PZ Suffix)

(1) The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not supported on this device.
(2) Throughout the remainder of this document, the TMS470R1A384 is referred to as either the full device name or as A384.
(3) SAE Standard J1850 Class B Data Communication Network Interface.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All other trademarks are the property of their respective owners.

The TMS470R1A384(2) devices are members of the Texas Instruments TMS470R1x family of general-purpose 16/32-bit reduced instruction set computer (RISC) microcontrollers. The A384 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The A384 utilizes the big-endian format where the most significant byte of a word is stored at the lowest-numbered byte and the least significant byte at the highest-numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low costs. The A384 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.

The A384 devices contain the following:

  • ARM7TDMI 16/32-bit RISC CPU
  • TMS470R1x system module (SYS) with 470+ enhancements
  • 384K-byte flash
  • 32K-byte SRAM
  • Zero-pin phase-locked loop (ZPLL) clock module
  • Analog watchdog (AWD) timer
  • Enhanced real-time interrupt (RTI) module
  • Interrupt expansion module (IEM)
  • Two serial peripheral interface (SPI) modules
  • Two serial communications interface (SCI) modules
  • Two standard CAN controllers (SCC)
  • Three inter-integrated circuit (I2C) modules
  • Class II serial interface B (C2SIb) module
  • 10-bit multi-buffered analog-to-digital converter (MibADC), with 12 input channels
  • High-end timer (HET) controlling 12 I/Os
  • External clock prescale (ECP)
  • Expansion bus module (EBM)
  • Up to 87 I/O pins and 1 input-only pin (PGE suffix only), up to 51 I/O pins and 1 input-only pin (PZ suffix only)

The functions performed by the 470+ system module (SYS) include:

  • Address decoding
  • Memory protection
  • Memory and peripherals bus supervision
  • Reset and abort exception management
  • Prioritization for all internal interrupt sources
  • Device clock control
  • Parallel signature analysis (PSA)

The enhanced real-time interrupt (RTI) module on the A384 has the option to be driven by the oscillator clock. This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).

The A384 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.

The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz. When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. For more detailed information on the flash, see the Flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).

The A384 device has ten communication interfaces: two SPIs, two SCIs, two SCCs, a C2SI, and three I2Cs. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. The C2SIb allows the A384 to transmit and receive messages on a class II network following an SAE J1850(3) standard. The I2C module is a multi-master communication module providing an interface between the A384 microcontroller and an I2C-compatible device via the I2C serial bus. The I2C supports both 100 Kbps and 400 Kbps speeds. For more detailed functional information on the SPI, SCI, and CAN peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197). For more detailed functional information on the I2C, see the TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number SPNU223). For more detailed functional information on the C2SI, see the TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214).

The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a standard HET. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).

The A384 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high- resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).

The A384 device has one 10-bit-resolution sample-and-hold MibADC. Each of the MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings, two of which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).

The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other A384 device modules. For more detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide (literature number SPNU212).

NOTE: ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal reference.

The expansion bus module (EBM) is a stand-alone module that supports the multiplexing of the GIO functions and the expansion bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module (EBM) Reference Guide (literature number SPNU222).

The A384 device also has an external clock prescaler (ECP) module that, when enabled, outputs a continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).

The TMS470R1A384(2) devices are members of the Texas Instruments TMS470R1x family of general-purpose 16/32-bit reduced instruction set computer (RISC) microcontrollers. The A384 microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The A384 utilizes the big-endian format where the most significant byte of a word is stored at the lowest-numbered byte and the least significant byte at the highest-numbered byte.

High-end embedded control applications demand more performance from their controllers while maintaining low costs. The A384 RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.

The A384 devices contain the following:

  • ARM7TDMI 16/32-bit RISC CPU
  • TMS470R1x system module (SYS) with 470+ enhancements
  • 384K-byte flash
  • 32K-byte SRAM
  • Zero-pin phase-locked loop (ZPLL) clock module
  • Analog watchdog (AWD) timer
  • Enhanced real-time interrupt (RTI) module
  • Interrupt expansion module (IEM)
  • Two serial peripheral interface (SPI) modules
  • Two serial communications interface (SCI) modules
  • Two standard CAN controllers (SCC)
  • Three inter-integrated circuit (I2C) modules
  • Class II serial interface B (C2SIb) module
  • 10-bit multi-buffered analog-to-digital converter (MibADC), with 12 input channels
  • High-end timer (HET) controlling 12 I/Os
  • External clock prescale (ECP)
  • Expansion bus module (EBM)
  • Up to 87 I/O pins and 1 input-only pin (PGE suffix only), up to 51 I/O pins and 1 input-only pin (PZ suffix only)

The functions performed by the 470+ system module (SYS) include:

  • Address decoding
  • Memory protection
  • Memory and peripherals bus supervision
  • Reset and abort exception management
  • Prioritization for all internal interrupt sources
  • Device clock control
  • Parallel signature analysis (PSA)

The enhanced real-time interrupt (RTI) module on the A384 has the option to be driven by the oscillator clock. This data sheet includes device-specific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).

The A384 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.

The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz. When in pipeline mode, the flash operates with a system clock frequency of up to 48 MHz. For more detailed information on the flash, see the Flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).

The A384 device has ten communication interfaces: two SPIs, two SCIs, two SCCs, a C2SI, and three I2Cs. The SPI provides a convenient method of serial interaction for high-speed communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The SCC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 megabit per second (Mbps). The SCC is ideal for applications operating in noisy and harsh environments (e.g., industrial fields) that require reliable serial communication or multiplexed wiring. The C2SIb allows the A384 to transmit and receive messages on a class II network following an SAE J1850(3) standard. The I2C module is a multi-master communication module providing an interface between the A384 microcontroller and an I2C-compatible device via the I2C serial bus. The I2C supports both 100 Kbps and 400 Kbps speeds. For more detailed functional information on the SPI, SCI, and CAN peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197). For more detailed functional information on the I2C, see the TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number SPNU223). For more detailed functional information on the C2SI, see the TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214).

The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a standard HET. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).

The A384 HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high- resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).

The A384 device has one 10-bit-resolution sample-and-hold MibADC. Each of the MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate groupings, two of which can be triggered by an external event. Each sequence can be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).

The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other A384 device modules. For more detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide (literature number SPNU212).

NOTE: ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal reference.

The expansion bus module (EBM) is a stand-alone module that supports the multiplexing of the GIO functions and the expansion bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module (EBM) Reference Guide (literature number SPNU222).

The A384 device also has an external clock prescaler (ECP) module that, when enabled, outputs a continuous external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).

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Technical documentation

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Type Title Date
* Data sheet TMS470R1A384 16/32-Bit RISC Flash Microcontroller datasheet (Rev. E) 21 May 2008
* Errata TMS470R1A384 TMS470 Microcontroller Silicon Errata (Rev. B) 29 Jan 2007
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 30 Mar 2023
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 30 Mar 2023
Functional safety information Hercules Diagnostic Library -TAU Installation Guide (Rev. B) PDF | HTML 08 Jan 2020
Functional safety information SafeTI™ Hercules™ Diagnostic Library Release Notes (Rev. A) 24 Sep 2019
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 03 Jun 2019
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 03 Jun 2019
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 19 Nov 2018
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 19 Nov 2018
Application note Interfacing the Embedded 12-Bit ADC in a TMS570LS31x/21x and RM4x Series MCUs (Rev. A) 20 Apr 2018
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 16 Jan 2018
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 16 Jan 2018
Application note Sharing FEE Blocks Between the Bootloader and the Application 07 Nov 2017
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 30 Sep 2017
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 30 Sep 2017
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 21 Jun 2017
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 21 Jun 2017
Application note Sharing Exception Vectors on Hercules™ Based Microcontrollers 27 Mar 2017
Application note How to Create a HALCoGen Based Project For CCS (Rev. B) 09 Aug 2016
Application note Using the CRC Module on Hercules™-Based Microcontrollers 04 Aug 2016
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 30 Apr 2016
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 30 Apr 2016
Application note High Speed Serial Bus Using the MibSPIP Module on Hercules-Based MCUs 22 Apr 2016
Application note JTAG Programmer Overview for Hercules-Based Microcontrollers 18 Nov 2015
Application note Interfacing Quadrature Encoders Using the High-End Timer on Hercules MCUs 19 Oct 2015
White paper Extending TI’s Hercules MCUs with the integrated flexible HET 29 Sep 2015
Functional safety information Foundational Software for Functional Safety 12 May 2015
Application note Triangle/Trapezoid Wave Generation Using PWM With Hercules N2HET 01 May 2015
Application note Nested Interrupts on Hercules ARM Cortex-R4/5-Based Microncontrollers 23 Apr 2015
Application note Interrupt and Exception Handling on Hercules ARM Cortex-R4/5-Based MCUs 20 Apr 2015
Application note Monitoring PWM Using N2HET 02 Apr 2015
Application note Hercules SCI With DMA 22 Mar 2015
Application note Limiting Clamp Currents on TMS470/TMS570 Digital and Analog Inputs (Rev. A) 08 Dec 2014
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 05 Nov 2014
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 05 Nov 2014
Functional safety information Migrating from RM48x or RM46x to RM42x Safety MCUs (Rev. A) 22 Sep 2014
Functional safety information Hercules TMS570LC/RM57Lx Safety MCUs Development Insights Using Debug and Trace 21 May 2014
Functional safety information Migrating From RM48x to RM46x Safety MCUs (Rev. A) 19 Feb 2014
Application note Interfacing TPS65381 With Hercules Microcontrollers (Rev. A) 14 Feb 2014
User guide Trace Analyzer User's Guide (Rev. B) 18 Nov 2013
Application note CAN Bus Bootloader for RM42 MCU 16 Sep 2013
Application note CAN Bus Bootloader for RM46 MCU 16 Sep 2013
Application note CAN Bus Bootloader for RM48x MCU 16 Sep 2013
Application note SPI Bootloader for Hercules RM42 MCU 16 Sep 2013
Application note SPI Bootloader for Hercules RM46 MCU 16 Sep 2013
Application note SPI Bootloader for Hercules RM48 MCU 16 Sep 2013
Application note UART Bootloader for Hercules RM42 MCU 16 Sep 2013
Application note UART Bootloader for Hercules RM46 MCU 16 Sep 2013
Application note UART Bootloader for Hercules RM48 MCU 16 Sep 2013
Application note Initialization of Hercules ARM Cortex-R4F Microcontrollers (Rev. D) 29 May 2013
Application note Reduction of Power Consumption for RM48L950 (Rev. A) 30 Oct 2012
Functional safety information Accelerating safety-certified motor control designs (Rev. A) 04 Oct 2012
Application note Initialization of the TMS570LS043x, 570LS033x & RM42L432 Hercules ARM Cortex-R4 26 Sep 2012
Application note Hercules Family Frequency Slewing to Reduce Voltage and Current Transients 05 Jul 2012
Application note Basic PBIST Configuration and Influence on Current Consumption (Rev. C) 12 Apr 2012
Application note Verification of Data Integrity Using CRC 17 Feb 2012
User guide HET Integrated Development Environment User's Guide (Rev. A) 17 Nov 2011
Functional safety information Important ARM Ltd Application Notes for TI Hercules ARM Safety MCUs 17 Nov 2011
Functional safety information Execution Time Measurement for Hercules ARM Safety MCUs (Rev. A) 04 Nov 2011
Application note Use of All 1'’s and All 0's Valid in Flash EEPROM Emulation 27 Sep 2011
Application note 3.3 V I/O Considerations for Hercules Safety MCUs (Rev. A) 06 Sep 2011
Functional safety information ADC Source Impedance for Hercules ARM Safety MCUs (Rev. B) 06 Sep 2011
Functional safety information Configuring a CAN Node on Hercules ARM Safety MCUs 06 Sep 2011
Functional safety information Configuring the Hercules ARM Safety MCU SCI/LIN Module for UART Communication (Rev. A) 06 Sep 2011
Functional safety information Leveraging the High-End Timer Transfer Unit on Hercules ARM Safety MCUs (Rev. A) 06 Sep 2011
Functional safety information Hercules™ Microcontrollers: Real-time MCUs for safety-critical products 02 Sep 2011
Application note NHET Getting Started (Rev. B) 30 Aug 2010
Functional safety information Generating Operating System Tick Using RTI on a Hercules ARM Safety MCU 13 Jul 2010
Functional safety information Usage of MPU Subregions on TI Hercules ARM Safety MCUs 10 Mar 2010
User guide TI Assembly Language Tools Enhanced High-End Timer (NHET) Assembler User's Guide 04 Mar 2010
White paper Discriminating between Soft Errors and Hard Errors in RAM White Paper 04 Jun 2008
White paper Using DMA to Double System Performance - White Paper 19 Jan 2007
User guide TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (Rev. C) 11 Feb 2005

Design & development

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Simulation model

RM44Lx22 ZWT; RM44Lx20 PGE and PZ BSDL Model

SPNM061.ZIP (9 KB) - BSDL Model
Simulation model

RM46Lx PGE BSDL Model

SPNM025.ZIP (11 KB) - BSDL Model
Simulation model

RM46Lx ZWT BSDL Model

SPNM026.ZIP (11 KB) - BSDL Model
Simulation model

RM48Lx PGE BSDL Model (Rev. A)

SPNM019A.ZIP (11 KB) - BSDL Model
Simulation model

RM48Lx ZWT BSDL Model (Rev. A)

SPNM017A.ZIP (11 KB) - BSDL Model
Simulation model

RM48x PGE IBIS Model (Silicon Revision B)

SPNM034.ZIP (255 KB) - IBIS Model
Simulation model

RM48x PGE IBIS Model (Silicon Revision C)

SPNM035.ZIP (255 KB) - IBIS Model
Simulation model

RM48x ZWT IBIS Model (Silicon Revision B)

SPNM040.ZIP (256 KB) - IBIS Model
Simulation model

RM48x ZWT IBIS Model (Silicon Revision C)

SPNM041.ZIP (256 KB) - IBIS Model
Package Pins Download
LQFP (PGE) 144 View options
LQFP (PZ) 100 View options

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  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

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