SMV512K32-SP

ACTIVE

Product details

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CFP (HFG) 76 517.8426 mm² 25.31 x 20.46
  • 20-ns Read, 13.8-ns Write Through Maximum Access Time
  • Functionally Compatible With Commercial
    512K x 32 SRAM Devices
  • Built-In EDAC (Error Detection and Correction) to Mitigate Soft Errors
  • Built-In Scrub Engine for Autonomous Correction
  • CMOS Compatible Input and Output Level, Three State Bidirectional
    Data Bus
    • 3.3 ±0.3-V I/O, 1.8 ±0.15-V CORE
  • Radiation Performance(1)
  • Uses Both Substrate Engineering and Radiation Hardened by Design (HBD)(2)
  • TID Immunity > 3e5 rad (Si)
  • SER < 5e-17 Upsets/Bit-Day (Core Using EDAC and Scrub)(3)
  • Latch up immunity > LET = 110 MeV (T = 398K)
  • Available in a 76-Lead Ceramic Quad Flatpack
  • Engineering Evaluation (/EM) Samples are Available(4)
  • (1) Radiation tolerance is a typical value based upon initial device qualification. Radiation Data and Lot Acceptance Testing is available – contact factory for details.
    (2) HardSIL™ technology and memory design under a license agreement with Silicon Space Technology (SST).
    (3) SER calculated using CREME96 for geosynchronous orbit,
    solar minimum.
    (4) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. no burn-in, etc.) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of –55°C to 125°C or operating life.

    • 20-ns Read, 13.8-ns Write Through Maximum Access Time
    • Functionally Compatible With Commercial
      512K x 32 SRAM Devices
    • Built-In EDAC (Error Detection and Correction) to Mitigate Soft Errors
    • Built-In Scrub Engine for Autonomous Correction
    • CMOS Compatible Input and Output Level, Three State Bidirectional
      Data Bus
      • 3.3 ±0.3-V I/O, 1.8 ±0.15-V CORE
    • Radiation Performance(1)
    • Uses Both Substrate Engineering and Radiation Hardened by Design (HBD)(2)
    • TID Immunity > 3e5 rad (Si)
    • SER < 5e-17 Upsets/Bit-Day (Core Using EDAC and Scrub)(3)
    • Latch up immunity > LET = 110 MeV (T = 398K)
  • Available in a 76-Lead Ceramic Quad Flatpack
  • Engineering Evaluation (/EM) Samples are Available(4)
  • (1) Radiation tolerance is a typical value based upon initial device qualification. Radiation Data and Lot Acceptance Testing is available – contact factory for details.
    (2) HardSIL™ technology and memory design under a license agreement with Silicon Space Technology (SST).
    (3) SER calculated using CREME96 for geosynchronous orbit,
    solar minimum.
    (4) These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. no burn-in, etc.) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of –55°C to 125°C or operating life.

    The SMV512K32 is a high performance asynchronous CMOS SRAM organized as 524,288 words by 32 bits. It is pin selectable between two modes: master or slave. The master device selection provides user defined autonomous EDAC scrubbing options. The slave device selection employs a scrub on demand feature that can be initiated by a master device. Three read cycles and four write cycles (described below) are available depending on the user needs.

    The SMV512K32 is a high performance asynchronous CMOS SRAM organized as 524,288 words by 32 bits. It is pin selectable between two modes: master or slave. The master device selection provides user defined autonomous EDAC scrubbing options. The slave device selection employs a scrub on demand feature that can be initiated by a master device. Three read cycles and four write cycles (described below) are available depending on the user needs.

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    Technical documentation

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    Type Title Date
    * Data sheet 16-Mb Radiation-Hardened SRAM datasheet (Rev. I) 02 Jan 2014
    * SMD SMV512K32-SP SMD 5962-11237 08 Jul 2016
    More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. A) 31 Aug 2023
    Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. A) PDF | HTML 17 Nov 2022
    Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 19 Oct 2022
    Selection guide TI Space Products (Rev. I) 03 Mar 2022
    Application note 16 MB Radiation-Hardened SRAM with EDAC to Mitigate Soft Errors (Rev. A) 02 Aug 2019
    E-book Radiation Handbook for Electronics (Rev. A) 21 May 2019
    User guide SMV512K32-CVAL User Guide 12 Jan 2012

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