Home Interface High-speed SerDes FPD-Link SerDes

SN65LVDS93A-Q1

ACTIVE

10MHz – 135MHz 28-bit Flat Panel Display Link LVDS SerDes Transmitter

SN65LVDS93A-Q1

ACTIVE

Product details

Function Serializer Color depth (bps) 24 Input compatibility LVCMOS Output compatibility LVDS Features Capable to Drive up to 10 meters STP Cable EMI reduction SSC Compatible Rating Automotive Operating temperature range (°C) -40 to 85
Function Serializer Color depth (bps) 24 Input compatibility LVCMOS Output compatibility LVDS Features Capable to Drive up to 10 meters STP Cable EMI reduction SSC Compatible Rating Automotive Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • AEC-Q100 Qualified with:
    • Temperature Grade 3: –40°C to 85°C
    • HBM ESD Classification 3
    • CDM ESD Classification C6
  • LVDS Display Series Interfaces Directly to LCD
    Display Panels With Integrated LVDS
  • Package: 14-mm × 6.1-mm TSSOP
  • 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect
    Directly to Low-Power, Low-Voltage Application
    and Graphic Processors
  • Transfer Rate up to 135 Mpps (Mega Pixel Per
    Second); Pixel Clock Frequency Range 10 MHz to
    135 MHz
  • Suited for Display Resolutions Ranging From
    HVGA up to HD With Low EMI
  • Operates From a Single 3.3-V Supply and 170
    mW (Typical) at 75 MHz
  • 28 Data Channels Plus Clock in Low-Voltage TTL
    to 4 Data Channels Plus Clock Out Low-Voltage
    Differential
  • Consumes Less Than 1 mW When Disabled
  • Selectable Rising or Falling Clock Edge Triggered
    Inputs
  • Support Spread Spectrum Clocking (SSC)
  • Compatible with all OMAP™ 2x, OMAP™ 3x, and
    DaVinci™ Application Processors
  • AEC-Q100 Qualified with:
    • Temperature Grade 3: –40°C to 85°C
    • HBM ESD Classification 3
    • CDM ESD Classification C6
  • LVDS Display Series Interfaces Directly to LCD
    Display Panels With Integrated LVDS
  • Package: 14-mm × 6.1-mm TSSOP
  • 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect
    Directly to Low-Power, Low-Voltage Application
    and Graphic Processors
  • Transfer Rate up to 135 Mpps (Mega Pixel Per
    Second); Pixel Clock Frequency Range 10 MHz to
    135 MHz
  • Suited for Display Resolutions Ranging From
    HVGA up to HD With Low EMI
  • Operates From a Single 3.3-V Supply and 170
    mW (Typical) at 75 MHz
  • 28 Data Channels Plus Clock in Low-Voltage TTL
    to 4 Data Channels Plus Clock Out Low-Voltage
    Differential
  • Consumes Less Than 1 mW When Disabled
  • Selectable Rising or Falling Clock Edge Triggered
    Inputs
  • Support Spread Spectrum Clocking (SSC)
  • Compatible with all OMAP™ 2x, OMAP™ 3x, and
    DaVinci™ Application Processors

The SN65LVDS93A-Q1 FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS94 and LCD panels with integrated LVDS receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN65LVDS93A-Q1 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.

The SN65LVDS93A-Q1 is characterized for operation over ambient air temperatures of –40°C to 85°C.

The SN65LVDS93A-Q1 FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS94 and LCD panels with integrated LVDS receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN65LVDS93A-Q1 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.

The SN65LVDS93A-Q1 is characterized for operation over ambient air temperatures of –40°C to 85°C.

Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 4
Type Title Date
* Data sheet SN65LVDS93A-Q1 FlatLink™ Transmitter datasheet (Rev. B) PDF | HTML 16 Apr 2015
Application note High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 09 Nov 2018
Application note AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (Rev. A) 03 Aug 2018
EVM User's guide LVDS83BTSSOPEVM User's Guide 13 Oct 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LVDS83BTSSOPEVM — LVDS83BT 10-135 MHz 28-bit LVDS Transmitter/Serializer Evaluation Module

The SN75LVDS83B transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted (...)
User guide: PDF
Not available on TI.com
Simulation model

SN65LVDS93A-Q1 IBIS Model

SLLM272.ZIP (25 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Package Pins Download
TSSOP (DGG) 56 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos