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LM3524D

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40V, 0.2A 350KHz PWM controller

Product details

Topology Full bridge Control mode Voltage Duty cycle (max) (%) 90 Switching frequency (max) (kHz) 350 Features Adjustable switching frequency, Error amplifier, Multi-topology, Synchronization pin Operating temperature range (°C) 0 to 125 Rating Catalog Gate drive (typ) (A) 0.2 Vin (max) (V) 40
Topology Full bridge Control mode Voltage Duty cycle (max) (%) 90 Switching frequency (max) (kHz) 350 Features Adjustable switching frequency, Error amplifier, Multi-topology, Synchronization pin Operating temperature range (°C) 0 to 125 Rating Catalog Gate drive (typ) (A) 0.2 Vin (max) (V) 40
SOIC (D) 16 59.4 mm² 9.9 x 6
  • Fully Interchangeable With Standard LM3524 Family
  • ±1% Precision 5V Reference With Thermal Shut-Down
  • Output Current to 200 mA DC
  • 60V Output Capability
  • Wide Common Mode Input Range for Error-Amp
  • One Pulse per Period (Noise Suppression)
  • Improved Max. Duty Cycle at High Frequencies
  • Double Pulse Suppression
  • Synchronize Through Pin 3

All trademarks are the property of their respective owners.

  • Fully Interchangeable With Standard LM3524 Family
  • ±1% Precision 5V Reference With Thermal Shut-Down
  • Output Current to 200 mA DC
  • 60V Output Capability
  • Wide Common Mode Input Range for Error-Amp
  • One Pulse per Period (Noise Suppression)
  • Improved Max. Duty Cycle at High Frequencies
  • Double Pulse Suppression
  • Synchronize Through Pin 3

All trademarks are the property of their respective owners.

The LM3524D family is an improved version of the industry standard LM3524. It has improved specifications and additional features yet is pin for pin compatible with existing 3524 families. New features reduce the need for additional external circuitry often required in the original version.

The LM3524D has a ±1% precision 5V reference. The current carrying capability of the output drive transistors has been raised to 200 mA while reducing VCEsat and increasing VCE breakdown to 60V. The common mode voltage range of the error-amp has been raised to 5.5V to eliminate the need for a resistive divider from the 5V reference.

In the LM3524D the circuit bias line has been isolated from the shut-down pin. This prevents the oscillator pulse amplitude and frequency from being disturbed by shut-down. Also at high frequencies (≃300 kHz) the max. duty cycle per output has been improved to 44% compared to 35% max. duty cycle in other 3524s.

In addition, the LM3524D can now be synchronized externally, through pin 3. Also a latch has been added to insure one pulse per period even in noisy environments. The LM3524D includes double pulse suppression logic that insures when a shut-down condition is removed the state of the T-flip-flop will change only after the first clock pulse has arrived. This feature prevents the same output from being pulsed twice in a row, thus reducing the possibility of core saturation in push-pull designs.

The LM3524D family is an improved version of the industry standard LM3524. It has improved specifications and additional features yet is pin for pin compatible with existing 3524 families. New features reduce the need for additional external circuitry often required in the original version.

The LM3524D has a ±1% precision 5V reference. The current carrying capability of the output drive transistors has been raised to 200 mA while reducing VCEsat and increasing VCE breakdown to 60V. The common mode voltage range of the error-amp has been raised to 5.5V to eliminate the need for a resistive divider from the 5V reference.

In the LM3524D the circuit bias line has been isolated from the shut-down pin. This prevents the oscillator pulse amplitude and frequency from being disturbed by shut-down. Also at high frequencies (≃300 kHz) the max. duty cycle per output has been improved to 44% compared to 35% max. duty cycle in other 3524s.

In addition, the LM3524D can now be synchronized externally, through pin 3. Also a latch has been added to insure one pulse per period even in noisy environments. The LM3524D includes double pulse suppression logic that insures when a shut-down condition is removed the state of the T-flip-flop will change only after the first clock pulse has arrived. This feature prevents the same output from being pulsed twice in a row, thus reducing the possibility of core saturation in push-pull designs.

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Technical documentation

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Type Title Date
* Data sheet LM2524D/LM3524D Regulating Pulse Width Modulator datasheet (Rev. E) 02 May 2013
Application note AN-288 System-Oriented DC-DC Conversion Techniques (Rev. B) 06 May 2013
Application note AN-715 LM385 Feedback Provides Regulator Isolation (Rev. A) 06 May 2013
Application note AN-694 A DMOS 3A, 55V, H-Bridge: The LMD18200 (Rev. C) 26 Apr 2013
Application note AN-272 Op Amp Booster Designs (Rev. B) 23 Apr 2013
Application note Applications of the LM3524 Pulse Width Modulator (Rev. B) 23 Apr 2013
More literature Die D/S LM3524D MDC Regulating Pulse Width Modulator 25 Sep 2012

Design & development

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Supported products & hardware

Supported products & hardware

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PWM controllers
LM3524D 40V, 0.2A 350KHz PWM controller
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SOIC (D) 16 View options

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